In the semiconductor manufacturing process, thousands of individual circuits or dies are formed in a series of steps whereby all of the circuits or dies are formed in parallel as the silicon wafer passes through various steps called the wafer fabrication process or “wafer fab” process. During the final steps of the wafer fab process, the individual circuits on the wafer can be tested through a wafer test system, which includes a wafer probing machine or “prober” and a tester, before they are separated or “diced” from the semiconductor wafer for packaging. The prober and tester work together to identify bad devices prior to packaging, which can save considerable expense on the front end that would otherwise be incurred by packaging bad devices that could have been detected at the wafer level.
With modern semiconductor wafers now spanning 12 inches in diameter (˜300 mm), wafers can include ten thousand or more devices. To test a wafer, each device must be identified and its position established so that each device can be correlated with the results of its respective electrical test during the probe test. Setting up the test program and making this correlation between the wafer image map and the test program can therefore be an elaborate and time-consuming process.
At present, the correlation of electrical test program to dies is done by mapping the relevant device-testing program and die identifier on the respective devices identified on the wafer image map. Although this needs to be done only once for a particular wafer type or wafer layout, at which time the mapping can be stored on the wafer tester or probe tester, enough of these one-time actions can nevertheless be very time-consuming in the factory environment.